The present invention relates to a lead free solder structure for the assembly of electronic components, and more particularly, to a lead free solder hierarchy for use in the assembly of electronic components.
Current controlled collapse chip connection (C4) or “flip chip” interconnection technology for joining chips to either ceramic or organic substrates typically employ a 97/3 Pb/Sn joining solder alloy as the ball-limiting metallurgy (BLM) on the chip side of the interconnect, and a suitable metallization, typically Ni/Au or Cr/Cu/Ni/Au, on the substrate side of the interconnect. This interconnect structure has to withstand temperature cycling. This temperature cycling can be a very stringent requirement, especially for chip on board interconnects where the chip is attached directly to a printed circuit board (PCB).
This is because the thermal coefficient of expansion (TCE) of the chip is around 3 parts per million (ppm), and that of a typical PCB is 15-18 ppm. For a ceramic substrate chip carrier, the TCE is much better matched, because the ceramic TCE lies in the range of 3.5 to 6.6 ppm. An underfill material, typically an epoxy, is often used to create a more reliable structure, particularly for chip-on-board schemes, where the strain caused by the high TCE mismatch is accommodated without causing fails.
A current problem now facing the industry is that lead elimination is a strategic requirement for all manufacturers. A lead free solution for chip attachment is actively being sought. One possible solution is to use a Sn rich alloy such as Sn/Ag/Cu or Sn/Ag/Bi, where the Sn comprises about 96% of the alloy. Such an alloy requires the use of a lower temperature for joining, in the range of 245 to 255° C. This is in contrast to temperatures as high as 340° C. for the Pb/Sn solder alloy.
An additional problem is that in manufacturing, joining the chip to a first level package, typically a ceramic or organic chip carrier, is the first step. This is followed by encapsulation with an underfill material and hat/lid attachment to form a module. After this first level interconnect assembly is complete, the module proceeds to the second level join. Second level join is the interconnect of the chip carrier to a PCB. This interconnect may be, for example, a ceramic ball grid array (CBGA), ceramic column grid array (CCGA), or plastic ball grid array (PBGA). In the Pb/Sn system, all this can be achieved easily, because the first level chip join to chip carrier step uses a 97/3 Pb/Sn solder alloy and requires a very high temperature, approximately 340° C. The second level chip carrier to PCB join step uses lower Pb compositions, such as eutectic Pb/Sn, and requires a much lower reflow temperature in the range of 200-220° C.
Therefore in the Pb system the chip C4 solder connection remains mostly undisturbed and in the solid state during subsequent processing. Using a Pb free, Sn rich alloy for both first level chip join and second level module to board join creates the problem of the chip BLM becoming molten during the second level attach processes and subsequent reflows such as may be required for rework.
Another problem is that when the first level SnAgCu solder interconnect becomes completely molten inside the underfill encapsulant, it produces large hydrostatic stresses on the walls of the encapsulant. These forces create strains large enough to cause delamination, cracking, rupture and finally, catastrophic fail of the encapsulant regions. This would likely cause shorting between the C4 solder connections, and potentially cause opens where the C4 solder connections may break away from their original as-joined position.
Whereas other alloy systems such as AuSn 80/20 may be employed to produce a solder temperature hierarchy, such solutions may not be widely applicable because of various manufacturing problems. Examples include the cost of the materials, brittle metallurgical properties and solder interactions which cause stress on the chip.
Therefore, notwithstanding the prior art solutions to the problem, there remains a need for a solder structure hierarchy which employs the use of alloys with a higher liquidus temperature for the first level C4 interconnections, and the use of alloys with a lower liquidus temperature for second level interconnections.
Accordingly, it is a purpose of the present invention to provide a lead free solder hierarchy structure for electronic packaging.
These and other purposes of the present invention will become more apparent after referring to the following description considered in conjunction with the accompanying drawings.